|Dr. Leon Stok
VP, Electronic Design Automation
IBM Systems Group
Title: From IoT to SoC
Abstract: Analysts project that by 2025, data from connected devices will yield actionable information that will drive potential economic value of as much as 11 trillion US$ . Sixty percent of existing enterprises are slated to adopt machine-to-machine IoT solutions over the next two years . IoT software platforms to enable, connect, secure, manage, and analyze such IoT solutions will be essential. This keynote will spell out what all of this means to the SoCs that will be the fabric of our IoT eco-systems.
 Unlocking the potential of the Internet of Things. McKinsey & Company, June 2015
 [The Forrester WaveTM: IoT Software Platforms, Q4 2016.
|Short Bio: Dr. Leon Stok is Vice President of IBM’s Electronic Design Automation group. Prior to this he held positions as director of EDA and executive assistant to IBM’s Senior Vice President of Technology and Intellectual Property and executive assistant to IBM’s Senior Vice President of the Technology group.
Dr. Stok studied electrical engineering at Eindhoven University of Technology, the Netherlands, from which he graduated with honors in 1986. He obtained a Ph.D. degree from Eindhoven University in 1991. He subsequently worked at IBM’s Thomas J. Watson Research Center as part of the team that developed BooleDozer, the IBM logic synthesis tool. He then managed IBM’s logic synthesis group and drove the development of PDS, IBM’s Placement-Driven Synthesis tool. Between 1999 and 2004, he led all of IBM’s design automation research as the Senior Manager of Design Automation at IBM Research.
Dr. Stok has published over sixty papers on many aspects of high level, architectural and logic synthesis, low power design, placement driven synthesis and on automatic placement and routing for schematic diagrams. He holds 13 patents in the area of EDA. He was elected an IEEE Fellow for the development and application of high-level and logic synthesis algorithm.
|Dr. Rafic Zein Makki
Senior Advisor, Mubadala Investment Company (On Assignment), Executive Fellow, GLOBALFOUNDRIES
Title: Building World Class R&D Capacity in Semiconductor Technology
Abstract: This talk provides an overview of the strategies and initiatives employed to develop a world-class R&D ecosystem in Abu Dhabi. The talk shows how industry, government, and academia came together to develop all the required components of the ecosystem, including infrastructure, human capital and access to leading-edge process technologies. The talk discusses the current state of the ecosystem and its future prospects.
|Short Bio: Rafic brings together a unique mix of national and international experience across academia, government and industry. He has held senior leadership positions in the US and Abu Dhabi including: Professor of Electrical and Computer Engineering, Director of Computer Engineering and President of the Faculty at the University of North Carolina at Charlotte; Dean of the College of Information Technology at UAE University; Vice President for Research at Masdar Institute of Science and Technology; Executive Director of Planning and Strategic Affairs of the Abu Dhabi Education Council; and his current position as Globalfoundries Executive Fellow. As Globalfoundries Executive Fellow, Rafic holds a leadership position in technology strategy and R&D. Rafic worked with the company’s different organizations to develop technology differentiation strategies and to advance a culture that promotes, nurtures and rewards innovation. Currently on secondment from Globalfoundries, Rafic is in Abu Dhabi, UAE, serving as senior advisor at Mubadala Investment Company, focusing on building university-industry capacity in applied R&D and technology transfer. Rafic is a member of the Board of Directors of the Semiconductor Research Corporation and serves on the executive committee of the SemiSynbio technology roadmap consortium. He is also serving as a member of the Community and Legacy Committee of the Special Olympics 2019 World Summer Games. Rafic holds a Ph.D. in Electrical Engineering (1983) from Tennessee Technological University. He has worked on research funded by DARPA, NSF, Intel, IBM, and Carolinas Medical Center, among others, and won several research awards including the 2002 First Citizen Research Scholar Medal and the ALCOA Outstanding Graduate Faculty Award.|
|Dr. Yervant Zorian
Chief Architect & Fellow, Synopsys
President of Synopsys Armenia
Title: Robustness Challenges in the Internet of Things
Abstract: The Internet of Things (IoT) is an extremely fragmented market and can be defined as anything from sensors to small servers. It is estimated that over 30 billion IoT devices will ship by 2020. The ability to sense countless amounts of information that communicates to the cloud is driving innovation into IoT applications, such as in wearable devices (for health, fitness or infotainment applications) and in machine-to-machine applications (in smart appliances, smart cities or commerce). It has become crucial for today’s IoT chips to use a range of new solutions during the design stage to ensure the robustness of manufacturing test, field reliability and security. DFT designers need to use new test and reliability solutions to enable power reductions during test, concurrent test, isolated debug and diagnosis, pattern porting, calibration, and uniform access. Moreover, the per unit IoT price remains a key factor in high volume production. Thus, minimizing the test cost while meeting the above technical issues is one of the major challenges of the IoT industry. This presentation, besides discussing the key trends and challenges of IoT, will cover solutions to handle the wide range of potential robustness challenges during all periods of the IoT lifecycle from design, post silicon bring-up, volume production, to in-system operation.
|Short Bio: Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.
Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia’s National Medal of Science.
He received an MS degree in Computer Engineering from the University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from the Wharton School of Business, University of Pennsylvania.
Prof. Simha Sethumadhavan
Associate Professor of Computer Science, Columbia University
Title: Design for Security: The Hardware-Up Principle
Abstract: In this talk, I will describe a new design principle for security: the hardware-up principle. Hardware-up security means that security must be engineered like hardware instead of being built like software. I will discuss how systems designed for security from hardware-up offer unique advantages unavailable in current protection systems: a smaller attack surface, energy-efficient execution, and the ability to reason about security compositionally.
I will illustrate hardware-up benefits through case studies.
For the first hardware-up case study, I will discuss how we can prevent attackers from taking advantage of unintentional hardware design flaws. Taking microarchitectural side channels as an example, I will discuss a new methodology that computer architects can use to reason micro architectural side-channels at processor design time.
Attackers can also intentionally weaken hardware to break systems. In the second case study, I will discuss how hardware itself can be created in a manner that provides assurance that its security has not been compromised due to design-time backdoors. I will describe the first static analysis tool for detecting hardware backdoors and our technique for silencing backdoors. I will mention a prototype built using our technique that incurs less than 8% area overhead and negligible performance overheads.
Finally, time permitting, I will describe a hardware malware detector, a first of its kind, that is vastly simpler to implement compared to a traditional software malware detector.
|Short Bio: Simha Sethumadhavan is an Associate Professor of Computer Science at Columbia University. Prof. Sethumadhavan’s research interests are in Computer Architecture and Computer Security. He is recipient of an Alfred P. Sloan Research Fellowship, the NSF CAREER award and a IBM co-operative research award. He has received six best paper awards and a graduate teaching award. His teams work on identifying new security vulnerabilities resulted in fixes to major products such as mobile phone processors and web browsers used by millions of users, and his work on hardware security is actively considered by standards organizations. He is also the founder of Chip Scan Inc. a company that specializes in technology for producing trustworthy hardware. He obtained his Ph.D. from the University of Texas, Austin, in 2007.|