Co-located Workshop

1st IFIP/IEEE International Workshop on Photonics SoC

PhotoSoC 2017

October 26, 2017, Abu Dhabi, UAE (Co-located with VLSI-SoC 2017)


Abe Elfadel, Masdar Institute, Khalifa University of Science and Technology, Abu Dhabi, UAU
Ian O’Connor, Lyon Institute of Nanotechnology, France
Jiang Xu, Hong Kong University of Science and Technology, China

Program Committee

Mahmoud Rasras, New York University, Abu Dhabi, UAE
Marcus Dahlem, Masdar Institute, Khalifa University of Science and Technology, Abu Dhabi, UAE
Jaime Viegas, Masdar Institute, Khalifa University of Science and Technology, Abu Dhabi, UAE
Ahmadreza Farsaei, Cadence, CA, USA
Sébastien Le Beux, Lyon Institute of Nanotechnology, France
Karlheinz Bock, TU Dresden, Germany
Sherif Hammouda, Mentor Graphics, Egypt

Workshop Objective and Scope

By the end of 2017, IP traffic will have exceeded the data rate of 100 ExaBytes (EB) per month with the expected cumulative average growth rate (CAGR) over the next few years being around 24%. The adoption of IPv6 in support of the Internet of Things (IoT) will result in CAGR of 74% of IPv6 traffic, reaching more than 50 EB per month in 2020. IoT will also drive the significant increase in machine-to-machine connections and traffic to reach the 10 EB mark in 2020. Integrated optics, and more particularly Si photonics, is the hardware technology most suitable for supporting such data traffic growth at all stages of the data path from end devices to servers, gateways, data centers, and WANs. The large-scale deployment of Si photonics technology is however still facing major challenges not unlike those that the IC industry faced in its early days. These challenges include a fragmented process technology; a high entry threshold for new designs; proprietary processes, components and tools; high design costs; and lack of skilled Si photonics designers.

The objective of the PhotoSoC 2017 workshop is to be an international forum for academia and industry to discuss these challenges and present the most recent advances in tackling them. The vision of the workshop is to systematically address the enablement of a low-cost, high-volume Si photonics roadmap for system design in support of the accelerated growth of end devices, data aggregators and network traffic. Industry and academia speakers who are deeply involved in the design and deployment of complex Si photonics solutions for data acquisition, communication, and processing will be invited to present their vision and latest research in Si photonics. The workshop will also feature refereed poster presentations on specialized topics in Si photonics.

Workshop Topics

The topics covered by the workshop include, but are not limited to, the following:

  1. Roadmaps toward Si photonics SoC
  2. CMOS-compatible Si photonics processes and components
  3. Opto-electronic design integration
  4. Packaging, assembly and 3D integration of Si photonics SoC
  5. Optical source integration for Si photonics SoC
  6. Test and reliability for Si photonics SoC
  7. Modeling and characterization of Si photonics components
  8. Design tools and methodologies for Si photonics SoC
  9. Hardware security for Si Photonics SoC
  10. Design examples: transceivers, sensors, processors, etc.

Call for Posters

You are invited to submit a two-page abstract in a PDF two-column format, including figures and references, to The abstract should follow the guidelines of the IEEE sponsored conference proceedings. The Word and LaTeX templates can be found here .

Abstracts will be peer-reviewed, and accepted ones will be called to submit a poster to the workshop. Each poster will be introduced with a 2-minute “pitch” given during the lecture session. PhotoSoC 2017 presentations and posters are not included in the VLSI-SoC 2017 proceedings or published on IEEE Xplore. The abstract submission deadline is Aug 31, 2017.

Workshop Advance Registration Fee: US$100, including refreshments and lunch. Workshop registration is through the VLSI-SoC 2017 secure registration  web site.